Flash memory devices typically program and erase data by using a tunneling phenomenon. Flash memory devices may be suitable for use as storage devices in portable media devices, because of their generally excellent data integrity, low power consumption, and strong durability from an external impact.
NAND flash memory devices, in which memory cells are connected in series, may provide superior integration because the size of the memory cells may be kept relatively small as compared to NOR flash memory devices, in which memory cells are connected in parallel. Thus, NAND flash memory devices may be more useful as mass storage devices. The storage capacity of NAND flash memory devices has increased to tens of gigabytes (Gb).
FIG. 1 is a block diagram illustrating a conventional NAND flash memory device 100. Referring to FIG. 1, the conventional NAND flash memory device 100 includes a controller 102, an address buffer circuit and latch circuit 104, a data input/output buffer circuit 106, a row decoder circuit 108, a column decoder circuit 110, a memory cell array 112, a sense amplifier and page buffer circuit 114, and a column gating circuit 116.
The controller 102 receives a plurality of control signals CLE, ALE, /CE, /RE, /WE, and /WP so as to generate mode control signals for controlling operations, such as a programming operation, an erasing operation and a reading operation of the conventional NAND flash memory device 100. In response to the mode control signals of the controller 102, the address buffer circuit and latch circuit 104 provides row addresses X-Add and column addresses Y-Add received through respective data input/output pins I/O to the row decoder circuit 108 and the column decoder circuit 110.
In response to the mode control signals of the controller 102, the row decoder circuit 108 selects a wordline of the memory cell array 112 by decoding the row addresses X-Add, and operates the selected wordline forming one string and the unselected wordlines, by applying a program voltage Vpgm, an erase voltage Verase, a read voltage Vread, or a pass voltage Vpass according to the programming operation, the erasing operation, or the reading operation. In response to the mode control signals of the controller 102, the column decoder circuit 110 decodes the column addresses Y-Add and transmits the decoded column addresses Y-Add to the column gating circuit 116.
During the reading operation, the sense amplifier and page buffer circuit 114 sense amplifies data of bitlines in a page including memory cells connected to the selected wordline of the memory cell array 112, and transmits the sense amplified data to the data input/output buffer circuit 106. During the programming operation, the sense amplifier and page buffer circuit 114 transmits data to be programmed to the bitlines, the data being received through the data input/output pins I/O and the data input/output buffer circuit 106. In response to the decoded column addresses Y-Add, the column gating circuit 116 transmits bitline data corresponding to a data input/output width, from among bitline data read by the sense amplifier and page buffer circuit 114, to the data input/output pins I/O through the data input/output buffer circuit 106.
A page in the memory cell array 112 may have a small block page configuration as illustrated in FIG. 2A or a large block page configuration as illustrated in FIG. 2B. The small block page configuration shown in FIG. 2A includes a 512 byte flash cell portion and a 16 byte spare flash cell portion, and the large block page configuration shown in FIG. 2B includes a 2048 byte flash cell portion and a 64 byte spare flash cell portion.
In a reading operation of such a conventional NAND flash memory device 100 of FIG. 1, tens of microseconds (μs) may be consumed in establishing a read address, sense amplifying memory cell data corresponding to the read address, and storing the sense amplified memory cell data in the sense amplifier and page buffer circuit 114. This is largely because of the characteristics of a string type NAND flash cell. Accordingly, the NAND flash memory device 100 may consume a relatively large amount of time performing a random access reading operation.